#SIXTYFORCE GRAPHICS PLUGINS SERIAL#
#SIXTYFORCE GRAPHICS PLUGINS MANUAL#

#SIXTYFORCE GRAPHICS PLUGINS SERIAL#

RDRAM is connected in serial (where transfers are done one bit at a time) while SDRAM uses a parallel connection (transfers multiple bits at a time). The type of RAM fitted in the board is called Rambus DRAM (RDRAM), this was just another design that competed against SDRAM on becoming the next standard.

I presume the CPU-RCP bus speed is either the RCP’s clock speed or the CPU one, but I haven’t been able to confirm that, yet. As a consequence, every component except the GPU will only find up to 4 MB. The system physically contains 4.5 MB of RAM, however, it’s connected using a 9-bit data bus where the 9th bit is reserved for the GPU (more details in the ‘Graphics’ section). Memory designĪpart from the UMA, the structure of RAM is a little bit complicated, so I’ll try to keep it simple. No DMA controller?ĭue to the unified memory architecture, the CPU no longer has direct access to RAM, so the GPU will be providing DMA functionality as well. The reason for choosing this design comes from the fact that it saves a considerable amount of production costs while, on the other side, it increments access contention if not managed properly. The component arbitrating its access is, in this case, the GPU. The way RAM is assembled follows the unified-memory architecture or ‘UMA’ where all available RAM is centralised in one place only and any component that requires RAM will access this shared location. Though it contains a dedicated register file and will speed up operations with 64-bit and 32-bit floating-point numbers. The VR4300 identifies it as a co-processor (CP1), however, the unit is fitted next to the ALU and it’s only accessed through the CPU’s internal ALU pipeline, meaning there’s no co-processing per se.

24 KB L1 cache: Divided into 16 KB for instructions and 8 KB for data.Īn internal Floating-point Unit (FPU) is also included in this package.

5-stage pipeline: Up to five instructions can be allocated for execution (a detailed explanation can be found in a previous article.

32-bit address bus: Up to 4 GB of physical memory can be addressed.

An internal 64-bit bus connected to an external 32-bit data bus: While double-words won’t degrade performance when operated internally, the CPU will still need to expend extra cycles to move 64-bit data throughout the system.

It’s worth mentioning that since MIPS II, load delay slots are gone for good, though branch delay ones still persist.

The instructions format is 32-bit long, independently of the mode. It features new instructions that operate double-words.

The MIPS III ISA: A RISC instruction set that succeeds MIPS II.

32 general-purpose registers: These are 32-bit wide in ‘32-bit mode’ and 64-bit wide in ‘64-bit mode’.

Consequently, large data can be operated more efficiently, although this also increments the size of the program considerably (for instance, pointers occupy 8 Bytes instead of 4). This includes registers, data and memory addresses - though only 40 bits are decoded in the latter case.

64-bit mode: Words are 64-bit long (called ‘double-words’).

32-bit mode: Traditional mode and the most common one for games.

The main processor is a NEC VR4300 that runs at 93.75 MHz, it’s a binary-compatible version of Silicon Graphics’ MIPS R4300i that features:

#SIXTYFORCE GRAPHICS PLUGINS MANUAL#

The result was a nice-looking console for the family… and a 500-page manual for the developer.ĭon’t worry, I promise you this article will not be that long… Enjoy! Nintendo’s goal was to give players the best graphics possible, for this it will partner with one of the biggest players in computer graphics to produce the ultimate graphics chip. Later ones reduced the number of chips required for AV encoding.ĭisk Drive connector is found on the back Motherboard with important parts labelled Diagram Main architecture diagram

Sixtyforce graphics plugins